Voltage supply circuit having an absorption unit and method for operating the same

ABSTRACT

A voltage supply unit including a regulator unit, a voltage divider and a first current mirror. The regulator unit is configured to receive a first voltage signal and a second voltage signal, and is configured to generate a third voltage signal. The voltage divider is connected between the first current mirror and the regulator unit, and controls the second voltage signal. The first current mirror is connected to the regulator unit, an input voltage supply and the voltage divider. The first current mirror is configured to generate a first current signal and a second current signal, the second current signal is mirrored from the first current signal, the first current signal is controlled by the third voltage signal and the second current signal controls an output voltage supply signal.

BACKGROUND

The semiconductor integrated circuit (IC) industry has produced a widevariety of devices to address issues in a number of different areas.Some of these devices have differing power requirements. As ICs havebecome smaller and more complex, operating voltages continue to decreasefor optimizing IC performance.

BRIEF DESCRIPTION OF THE DRAWINGS

One or more embodiments are illustrated by way of example, and not bylimitation, in the figures of the accompanying drawings, whereinelements having the same reference numeral designations represent likeelements throughout. It is emphasized that, in accordance with standardpractice in the industry various features may not be drawn to scale andare used for illustration purposes only. In fact, the dimensions of thevarious features in the drawings may be arbitrarily increased or reducedfor clarity of discussion. One or more embodiments illustrated in thedrawings, incorporated herein in their entirety, include the following:

FIG. 1 is a schematic diagram of a voltage supply unit in accordancewith one or more embodiments;

FIG. 2 is a schematic diagram of a voltage supply unit in accordancewith one or more embodiments;

FIG. 3 is a schematic diagram of a voltage supply unit in accordancewith one or more embodiments;

FIG. 4 is a schematic diagram of a voltage supply unit in accordancewith one or more embodiments;

FIG. 5 is a flow chart illustrating a method in accordance with one ormore embodiments; and

FIG. 6 is a flow chart illustrating a method in accordance with one ormore embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the disclosed subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are examples and are notintended to be limiting.

This description of the various embodiments is intended to be read inconnection with the accompanying drawings, which are to be consideredpart of the entire written description. In the description, relativeterms such as “before,” “after,” “above,” “below,” “up,” “down,” “top”and “bottom” as well as derivative thereof (e.g., “horizontally,”“downwardly,” “upwardly,” etc.) should be construed to refer to theorientation as then described or as shown in the drawing underdiscussion. These relative terms are for convenience of description anddo not require that the system be constructed or operated in aparticular orientation. Terms concerning attachments, coupling and thelike, such as “connected” and “interconnected,” refer to a relationshipwherein components are attached to one another either directly orindirectly through intervening components, unless expressly describedotherwise.

FIG. 1 is a schematic diagram of a voltage supply unit 100 in accordancewith one or more embodiments. Voltage supply unit 100 comprises aregulator unit 102, a cascode unit 104, a first absorption unit 106, afirst current mirror 108, a second absorption unit 110, a voltageclamping unit 112 and resistors R1 and R2. Voltage supply unit 100 isconnected to voltage supply VDDQ and a load unit 120. Voltage supplyunit 100 is configured to receive a first input signal VREF1 and voltagesupply VDDQ. Voltage supply unit 100 is configured to send an outputvoltage signal VO to load unit 120.

In some embodiments, output voltage signal VO is an intermediate voltagesignal that is less than voltage supply VDDQ. In some embodiments,output voltage supply VO is an intermediate voltage signal that isgreater than voltage supply VDDQ. In some embodiments, voltage supplyVDDQ is a high-voltage supply greater than at least one of VDD orintermediate voltage signal VO. In some embodiments, voltage supply VDDQis an integer multiple of VDD. In some embodiments, output voltagesignal VO is substantially equal to VDD. In some embodiments, outputvoltage signal VO is an integer multiple of VDD, but less than voltagesupply VDDQ. In some embodiments, voltage supply unit 100 is configuredto generate an output voltage signal VO substantially equal to 2*VDD. Insome embodiments, a low-voltage level refers to a voltage level lessthan voltage supply VDDQ and intermediate voltage signal VO. In someembodiments, VDD is characterized as a low-voltage level. In someembodiments, ground is characterized as a low-voltage level. In someembodiments, VDD is a voltage ranging from about 0.6 volts to about 1.2volts. In some embodiments, voltage supply VDDQ is substantially equalto 2.5 volts. In some embodiments, voltage supply VDDQ is substantiallyequal to 3.3 volts. In some embodiments, voltage supply VDDQ issubstantially equal to 5.0 volts.

In some embodiments, one or more of the semiconductor devices containedin voltage supply unit 100 comprise FinFET or Tri-gate devices. In someembodiments, one or more of the semiconductor devices contained involtage supply unit 100 are produced by a 10 nanometer (nm), 14 nm or 16nm semiconductor manufacturing process. In some embodiments, one or moreof the semiconductor devices contained in voltage supply unit 100 areproduced by a 65 nm or 90 nm semiconductor manufacturing process. Insome embodiments, one or more of the semiconductor devices contained involtage supply unit 100 comprise thin-gate devices or low-voltagedevices. In some embodiments, a thin-gate device comprises one or moresemiconductor devices in an integrated circuit where the equivalentoxide thickness of the one or more semiconductor devices is less thanthe equivalent oxide thickness of other semiconductor devices containedin the integrated circuit. In some embodiments, a low-voltage devicecomprises a semiconductor device in an integrated circuit where the Vddof the semiconductor device is less than the Vdd of other semiconductordevices contained in the integrated circuit.

In some embodiments, for a 10 nm semiconductor manufacturing process, athin-gate device comprises a semiconductor device with an equivalentoxide thickness ranging from about 5 angstroms (Å) to about 8 Å. In someembodiments, for a 10 nm semiconductor manufacturing process, alow-voltage device comprises a semiconductor device with a Vdd rangingfrom about 0.7 volts to about 0.9 volts.

In some embodiments, for a 16/14 nm semiconductor manufacturing process,a thin-gate device comprises a semiconductor device with an equivalentoxide thickness ranging from about 7 Å to about 10 Å. In someembodiments, for a 16/14 nm semiconductor manufacturing process, alow-voltage device comprises a semiconductor device with a Vdd rangingfrom about 0.8 volts to about 0.95 volts.

In some embodiments, for a 22/20 nm semiconductor manufacturing process,a thin-gate device comprises a semiconductor device with an equivalentoxide thickness ranging from about 8 Å to about 11 Å. In someembodiments, for a 22/20 nm semiconductor manufacturing process, alow-voltage device comprises a semiconductor device with a Vdd rangingfrom about 0.85 volts to about 1.0 volts.

In some embodiments, for a 32/28 nm semiconductor manufacturing process,a thin-gate device comprises a semiconductor device with an equivalentoxide thickness ranging from about 9 Å to about 12 Å. In someembodiments, for a 32/28 nm semiconductor manufacturing process, alow-voltage device comprises a semiconductor device with a Vdd rangingfrom about 0.9 volts to about 1.05 volts.

In some embodiments, for a 45/40 nm semiconductor manufacturing process,a thin-gate device comprises a semiconductor device with an equivalentoxide thickness ranging from about 10 Å to about 15 Å. In someembodiments, for a 45/40 nm semiconductor manufacturing process, alow-voltage device comprises a semiconductor device with a Vdd rangingfrom about 1.0 volts to about 1.1 volts.

In some embodiments, for a 65 nm semiconductor manufacturing process, athin-gate device comprises a semiconductor device with an equivalentoxide thickness ranging from about 11 Å to about 16 Å. In someembodiments, for a 65 nm semiconductor manufacturing process, alow-voltage device comprises a semiconductor device with a Vdd rangingfrom about 1.1 volts to about 1.2 volts.

In some embodiments, for a 90 nm semiconductor manufacturing process, athin-gate device comprises a semiconductor device with an equivalentoxide thickness ranging from about 12 Å to about 20 Å. In someembodiments, for a 90 nm semiconductor manufacturing process, alow-voltage device comprises a semiconductor device with a Vdd rangingfrom about 1.2 volts to about 1.5 volts.

Regulator unit 102 is connected to cascode unit 104, resistor R1 andresistor R2. Regulator unit 102 is configured to receive a first inputsignal VREF1 and a second input signal VFB. Regulator unit 102 isconfigured to provide a bias voltage to an n-type metal oxidesemiconductor (NMOS) transistor N1 and to control a source current I1received from cascode unit 104.

Regulator unit 102 comprises operational amplifier OP1, NMOS transistorN1 and capacitor C1. Operational amplifier OP1 is configured to receivefirst input signal VREF1 and second input signal VFB. The first inputsignal VREF1 is a reference voltage at the non-inverting terminal of theoperational amplifier OP1. The second input signal VFB is a voltage atthe inverting terminal of the operational amplifier OP1. Operationalamplifier OP1 is configured to send an output signal to NMOS transistorN1 and capacitor C1. The output signal of the operational amplifier OP1is a voltage applied to the gate of NMOS transistor N1 and capacitor C1.The operational amplifier OP1 includes two input terminals and oneoutput terminal. The first input terminal of the operational amplifierOP1 is connected to the source of the first input signal VREF1. Thesecond input terminal of the operational amplifier OP1 is connected tothe source of the second input signal VFB. In some embodiments,operational amplifier OP1 is configured in a negative feedbackconfiguration such that the source of the second input signal VFB isconnected to resistors R1 and R2 at node FB. The output of theoperational amplifier OP1 is connected to NMOS transistor N1 andcapacitor C1. In some embodiments, operational amplifier OP1 isconfigured in a comparator configuration. In some embodiments,operational amplifier OP1 includes a comparator device. In someembodiments, a p-type metal oxide semiconductor (PMOS transistor) isused in regulator unit 102.

The gate of NMOS transistor N1 is connected to operational amplifier OP1and is configured to receive the output signal of the operationalamplifier OP1. The drain of NMOS transistor N1 is connected to cascodeunit 104 (by the source of NMOS transistor N2). The source of NMOStransistor N1 is connected to ground. The regulator unit 102 isconfigured to maintain the gate voltage of NMOS transistor N1, whichcontrols the source current I1 received from cascode unit 104. In someembodiments, given a first input signal VREF1 and a second signal VFB,the regulator unit 102 is configured to control the gate voltage of NMOStransistor N1. The gate voltage of NMOS transistor N1 controls thesource current I1 received from cascode unit 104. In some embodiments,the output voltage signal VO of voltage supply unit 100 is fed back tothe operational amplifier OP1 by node FB and is compared with the firstinput signal VREF1 to provide a desired supply voltage (output voltagesignal VO).

Capacitor C1 is connected to the gate of NMOS transistor N1, the outputof operational amplifier OP1 and ground.

Cascode unit 104 is connected to regulator unit 102, first absorptionunit 106 and voltage clamping unit 112. Cascode unit 104 is connected tovoltage clamping unit 112 by node VC. Cascode unit 104 is configured toreceive a first bias signal B1, a second bias signal B2, source currentI1 and a clamp voltage from node VC. Cascode unit 104 is configured tosend source current I1 to regulator unit 102. Cascode unit 104 comprisesNMOS transistor N2 and NMOS transistor N3. In some embodiments, cascodeunit 104 prevents electrical over stress (EOS) in voltage supply unit100. In some embodiments, one or more PMOS transistors are used incascode unit 104.

The gate of NMOS transistor N2 is connected to the source of first biassignal B1. In some embodiments, first bias signal B1 is a bias voltagereceived from a bias generation circuit (not shown). In someembodiments, first bias signal B1 is a bias voltage substantially equalto VDD and is received from a bias generation circuit (not shown). Thedrain of NMOS transistor N2 is connected to the source of NMOStransistor N3 and to voltage clamping unit 112 (by the drain of PMOSdiode-connected transistor P8). In some embodiments, voltage clampingunit 112 reduces EOS in NMOS transistors N2 and N3. In some embodiments,voltage clamping unit 112 is configured to clamp the voltage at node VCat a first intermediate voltage. In some embodiments, the firstintermediate voltage is substantially equal to a voltage ranging betweenabout the first bias signal B1 and about the second bias signal B2. Insome embodiments, the first intermediate voltage is substantially equalto a voltage ranging between about VDD and about 2*VDD. In someembodiments, the first intermediate voltage is substantially equal to avoltage of about 1.5*VDD. The source of NMOS transistor N2 is connectedto the drain of NMOS transistor N1. In some embodiments, the voltageclamping unit 112 is implemented with more than one PMOS diode-connectedtransistors. In some embodiments, the voltage clamping unit 112 isimplemented with one or more NMOS diode-connected transistors.

The gate of NMOS transistor N3 is connected to the source of second biassignal B2. In some embodiments, second bias signal B2 is a bias voltagereceived from a bias generation circuit (not shown). In someembodiments, second bias signal B2 is a bias voltage substantially equalto 2*VDD and is received from a bias generation circuit (not shown). Thedrain of NMOS transistor N3 is connected to first absorption unit 106(by the drain of PMOS transistor P4). The source of NMOS transistor N3is connected to the drain of NMOS transistor N2 and to voltage clampingunit 112 (by the drain of NMOS transistor N4). In some embodiments,voltage clamping unit 112 reduces EOS in NMOS transistors N2 and N3. Insome embodiments, voltage clamping unit 112 is configured to clamp thevoltage at node VC at a first intermediate voltage. In some embodiments,the first intermediate voltage is substantially equal to a voltageranging between about the first bias signal B1 and about the second biassignal B2. In some embodiments, the first intermediate voltage issubstantially equal to a voltage ranging between about VDD and about2*VDD. In some embodiments, the first intermediate voltage issubstantially equal to a voltage of about 1.5*VDD. The body of NMOStransistor N3 is connected to the source of NMOS transistor N3.

First absorption unit 106 is connected to cascode unit 104 and firstcurrent mirror 108. First absorption unit 106 is configured to receive asource current I1 from first current mirror 108. First absorption unit106 is configured to send source current I1 to cascode unit 104. Firstabsorption unit 106 comprises PMOS transistor P3 and PMOS transistor P4.In some embodiments, first absorption unit 106 is configured to absorbone or more voltage drops from the voltage supply VDDQ. In someembodiments, one or more NMOS transistors are used in first absorptionunit 106.

The source of PMOS transistor P3 is connected to first current mirror108 (by the drain of PMOS transistor P2) and is configured to receivethe source current I1. The body of PMOS transistor P3 is connected tothe source of PMOS transistor P3. PMOS transistor P3 is connected in adiode configuration such that the gate of PMOS transistor P3 isconnected to the drain of PMOS transistor P3. The drain and gate of PMOStransistor P3 are connected to the source of PMOS transistor P4. Thedrain of PMOS transistor P3 is configured to send the source current I1to PMOS transistor P4.

The source of PMOS transistor P4 is connected to the drain of PMOStransistor P3 and is configured to receive the source current I1. Thebody of PMOS transistor P4 is connected to the source of PMOS transistorP4. PMOS transistor P4 is connected in a diode configuration such thatthe gate of PMOS transistor P4 is connected to the drain of PMOStransistor P4. The drain and gate of PMOS transistor P4 are connected tothe drain of NMOS transistor N3. The drain of PMOS transistor P4 isconfigured to send the source current I1 to NMOS transistor N3.

First current mirror 108 is connected to first absorption unit 106 andsecond absorption unit 110. First current mirror 108 is configured toreceive a source current I1 from voltage supply VDDQ. First currentmirror 108 is configured to send a source current I1 to first absorptionunit 106 and to send a supply current I2 to second absorption unit 110.In some embodiments, the supply current I2 is mirrored from the sourcecurrent I1. For example, source current I1 is used to set the gatevoltage of PMOS transistors P2 and P1; and the gate voltage of PMOStransistor P1 is used to set the supply current I2. In some embodiments,one or more NMOS transistors are used in first current mirror 108.

The source of PMOS transistor P2 is connected to voltage supply VDDQ andis configured to receive the source current I1. The body of PMOStransistor P2 is connected to the source of PMOS transistor P2. The gateof PMOS transistor P2 is connected to the gate of PMOS transistor P1.PMOS transistor P2 is connected in a diode configuration such that thegate of PMOS transistor P2 is connected to the drain of PMOS transistorP2. The drain and gate of PMOS transistor P2 are connected to the sourceof PMOS transistor P3. The drain of PMOS transistor P2 is configured tosend the source current I1 to the source of PMOS transistor P3.

The source of PMOS transistor P1 is connected to voltage supply VDDQ andis configured to receive the supply current I2. The body of PMOStransistor P1 is connected to the source of PMOS transistor P1. The gateof PMOS transistor P1 is connected to the gate of PMOS transistor P2.The drain of PMOS transistor P1 is connected to second absorption unit110 (by the source of PMOS transistor P5). The drain of PMOS transistorP1 is configured to send the supply current I2 to the source of PMOStransistor P5.

Second absorption unit 110 is connected to first current mirror 108,voltage clamping unit 112, resistor R1 and load unit 120. Secondabsorption unit 110 is configured to receive a supply current I2 fromfirst current mirror 108. Second absorption unit 110 is configured tosend supply current I2 to load unit 120 and resistor R1. Secondabsorption unit 110 comprises PMOS transistor P5. In some embodiments,second absorption unit 110 comprises more than one PMOS transistor P5.In some embodiments, second absorption unit 110 is configured to absorbone or more voltage drops from the voltage supply VDDQ. In someembodiments, one or more NMOS transistors are used in second absorptionunit 110. In some embodiments, second absorption unit 110 is optional.In some embodiments, second absorption unit 110 is not used where supplyvoltage VDDQ is substantially equal to 3*VDD and the output voltage VOis substantially equal to 2*VDD. In some embodiments, second absorptionunit 110 is not used where the difference between supply voltage VDDQand the output voltage VO is substantially equal to or less than VDD.

The source of PMOS transistor P5 is connected to first current mirror108 and is configured to receive the supply current I2. The body of PMOStransistor P5 is connected to the source of PMOS transistor P5. PMOStransistor P5 is connected in a diode configuration such that the gateof PMOS transistor P5 is connected to the drain of PMOS transistor P5.The drain and gate of PMOS transistor P5 are connected to the source ofNMOS transistor N4, resistor R1 and load unit 120. The drain of PMOStransistor P5 is configured to send the supply current I2 to load unit120 and resistor R1.

Voltage clamping unit 112 is connected to second absorption unit 110,resistor R1, load unit 120 and cascode unit 104. Voltage clamping unit112 comprises a diode-connected PMOS transistor P8. In some embodiments,voltage clamping unit 112 reduces EOS in NMOS transistors N2 and N3. Insome embodiments, voltage clamping unit 112 is configured to clamp thevoltage at node VC at a first intermediate voltage. In some embodiments,the first intermediate voltage is substantially equal to a voltageranging between about the first bias signal B1 and about the second biassignal B2. In some embodiments, the first intermediate voltage issubstantially equal to a voltage ranging between about VDD and about2*VDD. In some embodiments, the first intermediate voltage issubstantially equal to a voltage of about 1.5*VDD. The source of NMOStransistor N2 is connected to the drain of NMOS transistor N1. In someembodiments, the voltage clamping unit 112 is implemented with more thanone PMOS diode-connected transistors. In some embodiments, the voltageclamping unit 112 is implemented with one or more NMOS diode-connectedtransistors. In some embodiments, voltage clamping unit 112 is optional.

The source of PMOS transistor P8 is connected to second absorption unit110, resistor R1 and load unit 120. The body of PMOS transistor P8 isconnected to the source of PMOS transistor P8. PMOS transistor P8 isconnected in a diode configuration such that the gate of PMOS transistorP8 is connected to the drain of PMOS transistor P8. The drain and gateof PMOS transistor P8 are connected to the drain of NMOS transistor N2and the source of NMOS transistor N3.

Resistor R1 is connected to resistor R2, second absorption unit 110,voltage clamping unit 112, load unit 120 and regulator unit 102.Resistor R1 is connected to resistor R2 and regulator unit 102 by nodeFB. In some embodiments, resistor R1 and resistor R2 form an adjustablevoltage divider unit. Current I2 b flows through resistor R1. ResistorR1 and R2 form an adjustable voltage divider 114.

Resistor R2 is connected to resistor R1, regulator unit 102 and ground.One end of Resistor R2 is connected to resistor R1 and regulator unit102 by node FB. Another end of resistor R2 is connected to ground. Insome embodiments, resistor R2 and resistor R1 form an adjustable voltagedivider unit. Current I2 b flows through resistor R2. In someembodiments, resistor R2 is configured to be a variable resistor. Insome embodiments, resistor R2 and resistor R1 form an adjustable voltagedivider unit since resistor R2 is configured to be a variable resistor.For example, the voltage at node FB is represented by formula 1:V _(FB) =VO*R2/R1+R2  (1)Where V_(FB) is the voltage at node FB, VO is the output voltage signalVO of voltage supply unit 100, R1 is the value of resistor R1 and R2 isthe value of resistor R2.

As seen from formula 1, the value of resistor R2 controls the voltageV_(FB) at node FB. In some embodiments, resistor R2 controls the amountof voltage V_(FB) fed back to the regulator unit 102. In someembodiments, by adjusting the value of resistor R2, the amount ofvoltage V_(FB) fed back to the regulator unit 102 is also adjusted.

Voltage supply unit 100 is configured to output voltage signal VO toload unit 120. Voltage supply unit 100 is configured to output currentI2 a to load unit 120. In some embodiments, output voltage signal VO isan intermediate voltage signal less than voltage supply VDDQ. In someembodiments, voltage supply VDDQ is an integer multiple of VDD.

Load unit 120 comprises load unit 120 a, load unit 120 b, load unit 120c, and load capacitor CL. In some embodiments, load units 120 a, 120 band 120 c are load units configured with substantially different inputvoltage requirements, and voltage supply unit 100 is capable ofproviding the substantially different voltage requirements of load unit120. In some embodiments, load units 120 a, 120 b and 120 c are loadunits configured with substantially the same input voltage requirementsand voltage supply unit 100 is capable of providing the substantiallysimilar voltage requirements of load unit 120. In some embodiments,voltage supply VDDQ is substantially equal to 3*VDD, and the voltage ofload line L is substantially equal to 2*VDD.

Load unit 120 a is connected to VDDQ and load line L. In someembodiments, the voltage of load line L is substantially equal to 2*VDD.

Load unit 120 b is connected to VDDC and load line L. In someembodiments, the voltage of load line L is substantially equal to 2*VDD.In some embodiments, voltage supply VDDC is substantially equal to VDD.

Load unit 120 c is connected to load line L and ground. In someembodiments, the voltage of load line L is substantially equal to 2*VDD.

Load capacitor CL is connected to load line L and ground. In someembodiments, the voltage of load line L is substantially equal to 2*VDD.

FIG. 2 is a schematic diagram of a voltage supply unit 200 in accordancewith one or more embodiments. Voltage supply unit 200 is an embodimentof the voltage supply unit 100 shown in FIG. 1. As shown in FIG. 2,similar elements have a same reference number as shown in FIG. 1. Incomparison with voltage supply unit 100 (shown in FIG. 1), voltagesupply unit 200 also includes a third absorption unit 202, NMOStransistor N6 and a second current mirror 204. In some embodiments,third absorption unit 202, NMOS transistor N6 and a second currentmirror 204 provide stability to voltage supply unit 200 during low-loador no-load conditions.

Third absorption unit 202 is connected to second absorption unit 110,voltage clamping unit 112, resistor R1 and load unit 120 by load line L.Third absorption unit 202 is also connected to NMOS transistor N6. Thirdabsorption unit 202 is configured to receive a current I3 from load lineL. Third absorption unit 202 is configured to send current I3 to NMOStransistor N6. Third absorption unit 202 comprises PMOS transistor P6and PMOS transistor P7. In some embodiments, third absorption unit 202is configured to absorb one or more voltage drops from the load line L.In some embodiments, one or more NMOS transistors are used in thirdabsorption unit 202.

The source of PMOS transistor P6 is connected to second absorption unit110, voltage clamping unit 112, resistor R1 and load unit 120 by loadline L and is configured to receive current I3. The body of PMOStransistor P6 is connected to the source of PMOS transistor P6. PMOStransistor P6 is connected in a diode configuration such that the gateof PMOS transistor P6 is connected to the drain of PMOS transistor P6.The drain and gate of PMOS transistor P6 are connected to the source ofPMOS transistor P7. The drain of PMOS transistor P6 is configured tosend the current I3 to PMOS transistor P7.

The source of PMOS transistor P7 is connected to the drain of PMOStransistor P6 and is configured to receive the current I3. The body ofPMOS transistor P7 is connected to the source of PMOS transistor P7.PMOS transistor P7 is connected in a diode configuration such that thegate of PMOS transistor P7 is connected to the drain of PMOS transistorP7. The drain and gate of PMOS transistor P7 are connected to the drainof NMOS transistor N6. The drain of PMOS transistor P7 is configured tosend the current I3 to NMOS transistor N6.

The gate of NMOS transistor N6 is connected to the source of third biassignal B3. In some embodiments, third bias signal B3 is a bias voltagereceived from a bias generation circuit (not shown). In someembodiments, third bias signal B3 is a bias voltage substantially equalto VDD and is received from a bias generation circuit (not shown). Thedrain of NMOS transistor N6 is connected to third absorption unit 202(by the drain of PMOS transistor P7). In some embodiments, NMOStransistor N6 reduces EOS in third absorption unit 202 and secondcurrent mirror 204. The source of NMOS transistor N6 is connected to thedrain of NMOS transistor N5.

Second current mirror 204 is connected to NMOS transistor N6. Secondcurrent mirror 204 is configured to receive a current from currentsource CS1 and voltage supply VDD. Second current mirror 204 isconfigured to receive a current I3 from NMOS transistor N6 and thirdabsorption unit 202. In some embodiments, the current I3 is mirroredfrom the current received from the current source CS1. For example,current received from the current source CS1 is used to set the gatevoltage of NMOS transistors N7 and N5; and the gate voltage of NMOStransistor N5 is used to set the value of current I3. In someembodiments, one or more PMOS transistors are used in second currentmirror 204.

Current source CS1 is connected to voltage supply VDD, the drain of NMOStransistor N7 and resistor Rb. Current source CS1 is configured toprovide a reference electric current for second current mirror 204.

The drain of NMOS transistor N7 is configured to receive current fromcurrent source CS1. The gate of NMOS transistor N7 is connected to thegate of NMOS transistor N5 (by resistor Rb). NMOS transistor N7 isconnected in a diode configuration such that the gate of NMOS transistorN7 is connected to the drain of NMOS transistor N7. The source of NMOStransistor N7 is connected to ground.

Resistor Rb is connected to current source CS1, the gate and drain ofNMOS transistor N7, the gate of NMOS transistor N5, and capacitor C2. Insome embodiments, resistor Rb and capacitor C2 form a low pass filter tofilter the signal received from NMOS transistor N7 and current sourceCS1.

Capacitor C2 is connected to the gate of NMOS transistor N5 and resistorRb.

The drain of NMOS transistor N5 is configured to receive the current I3from the source of NMOS transistor N6. The gate of NMOS transistor N5 isconnected to the gate of NMOS transistor N7 (by resistor Rb). The sourceof NMOS transistor N5 is connected to ground. In some embodiments,during a high-load condition, NMOS transistor N5 is slightly biased andadjusts the current I3. In some embodiments, during a low-loadcondition, NMOS transistor N5 is heavily biased and adjusts the currentI3. In some embodiments, during a no-load condition, NMOS transistor N5is heavily biased and adjusts the current I3. In some embodiments,during a low-load or no-load condition, NMOS transistor N5 is astability enhancement device by controlling the current I3.

FIG. 3 is a schematic diagram of a voltage supply unit 300 in accordancewith one or more embodiments. Voltage supply unit 300 is an embodimentof the voltage supply unit 200 shown in FIG. 2. As shown in FIG. 3,similar elements have a same reference number as shown in FIG. 2. Incomparison with voltage supply unit 200 (shown in FIG. 2), voltagesupply unit 300 includes first absorption unit 306 in place of firstabsorption unit 106. In comparison with voltage supply unit 200 (shownin FIG. 2), voltage supply unit 300 includes voltage clamping unit 312in place of voltage clamping unit 112.

First absorption unit 306 is connected to cascode unit 104 and firstcurrent mirror 108. First absorption unit 306 is configured to receive asource current I1 from first current mirror 108. First absorption unit306 is configured to send source current I1 to cascode unit 104. Firstabsorption unit 306 comprises diode D1 and diode D2. In someembodiments, first absorption unit 306 is configured to absorb one ormore voltage drops from the voltage supply VDDQ.

The anode of diode D1 is connected to first current mirror 108 (by thedrain of PMOS transistor P2) and is configured to receive the sourcecurrent I1. The cathode of diode D1 is configured to send the sourcecurrent I1 to the anode of diode D2.

The anode of diode D2 is connected to the cathode of diode D1 and isconfigured to receive the source current I1. The cathode of D2 isconfigured to send the source current I1 to NMOS transistor N3.

Voltage clamping unit 312 is connected to second absorption unit 110,resistor R1, load unit 120 and cascode unit 104. Voltage clamping unit312 comprises diode D3. In some embodiments, voltage clamping unit 312reduces EOS in NMOS transistors N2 and N3. In some embodiments, voltageclamping unit 312 is configured to clamp the voltage at node VC at afirst intermediate voltage. In some embodiments, the first intermediatevoltage is substantially equal to a voltage ranging between about thefirst bias signal B1 and about the second bias signal B2. In someembodiments, the first intermediate voltage is substantially equal to avoltage ranging between about VDD and about 2*VDD. In some embodiments,the first intermediate voltage is substantially equal to a voltage ofabout 1.5*VDD. The source of NMOS transistor N2 is connected to thedrain of NMOS transistor N1. In some embodiments, voltage clamping unit312 is optional.

FIG. 4 is a schematic diagram of a voltage supply unit 400 in accordancewith one or more embodiments. Voltage supply unit 400 is an embodimentof the voltage supply unit 100 shown in FIG. 1. As shown in FIG. 4,similar elements have a same reference number as shown in FIG. 1. Incomparison with voltage supply unit 100 (shown in FIG. 1), voltagesupply unit 400 does not include voltage clamping unit 112. Incomparison with voltage supply unit 100 (shown in FIG. 1), voltagesupply unit 400 includes cascode unit 404 in place of cascode unit 104.In comparison with voltage supply unit 100 (shown in FIG. 1), voltagesupply unit 400 includes first absorption unit 406 in place of firstabsorption unit 106. In comparison with voltage supply unit 100 (shownin FIG. 1), voltage supply unit 400 includes second absorption unit 410in place of second absorption unit 110.

In comparison with voltage supply unit 100 (shown in FIG. 1), voltagesupply unit 400 is configured to generate output voltage signal VO asrepresented by formula 2:VO=X*VDD  (2)Where VO is the output voltage signal VO of voltage supply unit 400, Xis a positive number and VDD is a voltage supply. In some embodiments, Xis an integer.

Cascode unit 404 includes three or more NMOS transistor devices N11, . .. N1X (where X is an integer corresponding to the number of NMOStransistor devices) connected in the same configuration as that shown inFIG. 1. In comparison with cascode unit 104 (shown in FIG. 1), cascodeunit 404 does not include voltage clamping unit 112. Each of the NMOStransistor devices N11, . . . N1X are configured to receive acorresponding bias signal B1, . . . a Xth bias signal B1X. In someembodiments, the function of the cascode unit 404 is the same as cascodeunit 104 (shown in FIG. 1). As shown in equation 2, the value of integerX determines the number of NMOS transistor devices N11, . . . N1X andbias input signals B11, . . . B1X in cascode unit 400.

In some embodiments, if the integer X is equal to 3, then the outputvoltage signal VO is substantially equal to 3*VDD and three NMOStransistors N11, N12 and N13 are used in cascode unit 404.

In this example, the first intermediate voltage between NMOS transistorN11 and N12 is substantially equal to a voltage ranging between aboutthe first bias signal B11 and about the second bias signal B12. In someembodiments, the first intermediate voltage is substantially equal to avoltage ranging between about VDD and about 2*VDD. In some embodiments,the first intermediate voltage is substantially equal to a voltage ofabout 1.5*VDD. In this example, the second intermediate voltage betweenNMOS transistor N12 and N13 is substantially equal to a voltage rangingbetween about the second bias signal B12 and about the third bias signalB13. In some embodiments, the second intermediate voltage issubstantially equal to a voltage ranging between about 2*VDD and about3*VDD. In some embodiments, the second intermediate voltage issubstantially equal to a voltage of about 2.5*VDD. In some embodiments,cascode unit 404 prevents electrical over stress (EOS) in voltage supplyunit 400. In some embodiments, one or more PMOS transistors are used incascode unit 404.

First absorption unit 406 includes diode devices D11, . . . D1 n (wheren is an integer corresponding to the number of diode devices) in placeof PMOS transistors P3 and P4.

The anode of diode D11 is connected to first current mirror 108 (by thedrain of PMOS transistor P2) and is configured to receive the sourcecurrent I1. The cathode of diode D11 is configured to send the sourcecurrent I1 to the anode of diode D1 n.

The anode of diode D1 n is connected to the cathode of diode D11 and isconfigured to receive the source current I1. The cathode of diode D1 nis configured to send the source current I1 to NMOS transistor N1X.

In some embodiments, the function of the first absorption unit 406 isthe same as first absorption unit 106 (shown in FIG. 1). In someembodiments, first absorption unit 406 is configured to absorb one ormore voltage drops from the voltage supply VDDQ. For example, where VDDQis substantially equal to 4*VDD, and output voltage signal VO issubstantially equal to 2*VDD, then the integer n is equal to 3 or 4 suchthat first absorption unit 406 includes 3 diodes (D11, D12 and D13) or 4diodes (D11, D12, D13 and D14). For example, where VDDQ is substantiallyequal to 3*VDD, and output voltage signal VO is substantially equal to2*VDD, then the integer n is equal to 2 or 3 such that first absorptionunit 406 includes 2 diodes (D11 and D12) or 3 diodes (D11, D12 and D13).

Second absorption unit 410 includes diode devices D21, . . . D2 m (wherem is an integer corresponding to the number of diode devices) in placeof PMOS transistor P5.

The anode of diode D21 is connected to first current mirror 108 (by thedrain of PMOS transistor P1) and is configured to receive the supplycurrent I2. The cathode of diode D21 is configured to send the supplycurrent I2 to the anode of diode D2 m.

The anode of diode D2 m is connected to the cathode of diode D21 and isconfigured to receive the supply current I2. The cathode of diode D2 mis configured to send the supply current I2 to load unit 120 andresistor R1.

In some embodiments, the function of the second absorption unit 410 isthe same as second absorption unit 110 (shown in FIG. 1). In someembodiments, second absorption unit 410 is configured to absorb one ormore voltage drops from the voltage supply VDDQ and to reduce EOS onPMOS transistor P1. For example, where VDDQ is substantially equal to4*VDD, and output voltage signal VO is substantially equal to 2*VDD,then the integer n is equal to 3 or 4 such that second absorption unit410 includes 3 diodes (D21, D22 and D23) or 4 diodes (D21, D22, D23 andD24). For example, where VDDQ is substantially equal to 3*VDD, andoutput voltage signal VO is substantially equal to 2*VDD, then theinteger n is equal to 2 or 3 such that second absorption unit 410includes 2 diodes (D21 and D22) or 3 diodes (D21, D22 and D23).

FIG. 5 is a flow chart illustrating a method 500 of generating anintermediate voltage level from a high voltage level in a voltage supplyunit in accordance with one or more embodiments. Method 500 begins withoperation 502 in which a first current signal of a current mirror iscontrolled by a first operating voltage of a regulator unit.

In operation 504, a first voltage drop and a second voltage drop fromthe high voltage level are absorbed. In some embodiments, the firstvoltage drop is absorbed by a first P-type transistor and the secondvoltage drop is absorbed by a second P-type transistor.

In operation 506, the electrical over stress in the voltage supply unitis reduced by controlling a first bias voltage of a first N-typetransistor and controlling a second bias voltage of a second N-typetransistor.

In operation 508, the electrical over stress in the first N-typetransistor and the second N-type transistor are reduced by clamping avoltage level between the first N-type transistor and the second N-typetransistor to an intermediate biasing voltage level. In someembodiments, the intermediate biasing voltage level is between the firstbias voltage and the second bias voltage.

In operation 510, a first operating voltage of the current mirror iscontrolled by the first current signal.

In operation 512, a second operating voltage of the current mirror iscontrolled by the first operating voltage of the current mirror.

In operation 514, a second current signal of the current mirror iscontrolled by the second operating voltage of the current mirror.

In operation 516, a feedback voltage signal is controlled by anadjustable voltage divider.

FIG. 6 is a flow chart illustrating a method 600 of controlling a firstoperating voltage of a regulator unit in accordance with one or moreembodiments. Method 600 is an embodiment of operation 502 shown inmethod 500. Method 600 begins with operation 602 in which a firstvoltage signal is received. In some embodiments, the first voltagesignal is a reference voltage.

In operation 604, a second voltage signal is received. In someembodiments, the second voltage signal is substantially equal to thefeedback voltage signal.

In operation 606, the first operating voltage of the regulator unit issent.

One aspect of this description relates to a voltage supply unitcomprising a regulator unit, a voltage divider and a first currentmirror. The regulator unit is configured to receive a first voltagesignal and a second voltage signal, and is configured to generate athird voltage signal. The voltage divider is connected between the firstcurrent mirror and the regulator unit, and the voltage divider controlsthe second voltage signal. The first current mirror is connected to theregulator unit, an input voltage supply and the voltage divider. Thefirst current mirror is configured to generate a first current signaland a second current signal, the second current signal is mirrored fromthe first current signal, the first current signal is controlled by thethird voltage signal and the second current signal controls an outputvoltage supply signal.

Another aspect of this description relates a voltage supply unitcomprising a regulator unit, an adjustable voltage divider and a firstcurrent mirror. The regulator unit is configured to receive a firstvoltage signal and a second voltage signal, and is configured togenerate a third voltage signal. The adjustable voltage divider isconnected between the first current mirror and the regulator unit, andthe adjustable voltage divider controls the second voltage signal. Thefirst current mirror is connected to the regulator unit, an inputvoltage supply and the adjustable voltage divider. Further, the firstcurrent mirror is configured to generate a first current signal and asecond current signal, the second current signal is mirrored from thefirst current signal, the first current signal is controlled by thethird voltage signal, and the second current signal controls an outputvoltage supply signal.

Still another aspect of this description relates to a method ofgenerating an output voltage level from an input voltage level in avoltage supply unit, the method comprising controlling a first currentsignal of a current mirror by a first operating voltage of a regulatorunit, controlling a first operating voltage of the current mirror by thefirst current signal, controlling a second operating voltage of thecurrent mirror by the first operating voltage of the current mirror,controlling a second current signal of the current mirror by the secondoperating voltage of the current mirror and controlling a feedbackvoltage signal by an adjustable voltage divider, wherein the outputvoltage level is less than the input voltage level.

It will be readily seen by one of ordinary skill in the art that thedisclosed embodiments fulfill one or more of the advantages set forthabove. After reading the foregoing specification, one of ordinary skillwill be able to affect various changes, substitutions of equivalents andvarious other embodiments as broadly disclosed herein. It is thereforeintended that the protection granted hereon be limited only by thedefinition contained in the appended claims and equivalents thereof.

What is claimed is:
 1. A voltage supply unit, comprising: a regulatorunit configured to receive a first voltage signal and a second voltagesignal, and configured to generate a third voltage signal; a voltagedivider electrically connected to the regulator unit, wherein thevoltage divider is configured to control the second voltage signal; acurrent mirror electrically connected to the regulator unit, an inputvoltage supply, and the voltage divider, wherein the current mirror isconfigured to generate a first current signal and a second currentsignal wherein the second current signal is mirrored from the firstcurrent signal, the first current signal is controlled by the thirdvoltage signal, and an output voltage supply signal is controlled by thesecond current signal; and an absorption unit, wherein a first terminalof the absorption unit is electrically connected to the current mirror,and a second terminal of the absorption unit is electrically connectedto an electrical overload prevention unit.
 2. The voltage supply unit ofclaim 1, wherein the voltage divider comprises an adjustable resistor,wherein the adjustable resistor is configured to adjust the secondvoltage signal.
 3. The voltage supply unit of claim 1, wherein theregulator unit comprises a N-type transistor, wherein a first terminalof the N-type transistor is configured as a first input node to receivethe third voltage signal, a second terminal of the N-type transistor isconfigured as a second input node to receive the first current signal,and a third terminal of the N-type transistor is coupled to a groundterminal.
 4. The voltage supply unit of claim 1, wherein the electricaloverload prevention unit comprises a cascode unit configured to preventelectrical overload stress in the voltage supply unit, the cascode unitcomprising a first N-type transistor and a second N-type transistor,wherein: a first terminal of the first N-type transistor is configuredas a first input node to receive a first bias voltage signal, a secondterminal of the first N-type transistor is configured as a second inputnode to receive the first current signal, a first terminal of the secondN-type transistor is configured as a third input node to receive asecond bias voltage signal, a second terminal of the second N-typetransistor is configured as a fourth input node to receive the firstcurrent signal from the first N-type transistor, and a third terminal ofthe second N-type transistor is electrically connected to the regulatorunit.
 5. The voltage supply unit of claim 4, further comprising avoltage clamping unit electrically connected to the second terminal ofthe second N-type transistor, wherein the voltage clamping unit isconfigured to maintain an intermediate voltage signal, wherein a levelof the intermediate voltage signal is between a level of the first biasvoltage signal and a level of the second bias voltage signal.
 6. Thevoltage supply unit of claim 5, wherein the voltage clamping unitcomprises: a P-type transistor wherein a first terminal of the P-typetransistor is configured to receive the output voltage supply signal, asecond terminal of the P-type transistor is electrically connected to athird terminal of the first N-type transistor and the second terminal ofthe second N-type transistor, and a third terminal of the P-typetransistor is electrically connected to the second terminal of theP-type transistor.
 7. The voltage supply unit of claim 5, wherein thevoltage clamping unit comprises a diode, wherein a first terminal of thediode is configured to receive the output voltage supply signal, and asecond terminal of the diode is electrically connected to a thirdterminal of the first N-type transistor and the second terminal of thesecond N-type transistor.
 8. The voltage supply unit of claim 1 whereinthe absorption unit is configured to absorb one or more voltage dropsfrom the input voltage supply, the absorption unit comprising: a firstterminal of a first P-type transistor configured as a first input nodeto receive the first current signal from the current mirror, a secondterminal of the first P-type transistor configured as a first outputnode electrically connected to a second P-type transistor, a thirdterminal of the first P-type transistor electrically connected to thesecond terminal of the first P-type transistor, a fourth terminal of thefirst P-type transistor electrically connected to the first terminal ofthe first P-type transistor, a first terminal of the second P-typetransistor configured as a second input node to receive the firstcurrent signal from the second terminal of the first P-type transistor,a second terminal of the second P-type transistor configured as a secondoutput node electrically connected to the electrical overload preventionunit, a third terminal of the second P-type transistor electricallyconnected to the second terminal of the second P-type transistor, and afourth terminal of the second P-type transistor electrically connectedto the first terminal of the second P-type transistor.
 9. The voltagesupply unit of claim 1 wherein the absorption unit is configured toabsorb one or more voltage drops from the input voltage supply, theabsorption unit comprising a first diode and a second diode, wherein:the first diode comprises: a first diode first terminal is configured asa first input node to receive the first current signal from the currentmirror, and a first diode second terminal configured as a first outputnode electrically connected to the second diode, and the second diodecomprises: a second diode first terminal configured as a second inputnode to receive the first current signal from the first diode, and asecond diode second terminal configured as a second output nodeelectrically connected to the regulator unit.
 10. A voltage supply unit,comprising: a regulator unit configured to receive a first voltagesignal and a second voltage signal, and generate a third voltage signal;an adjustable voltage divider electrically connected to the regulatorunit; a current mirror electrically connected to the regulator unit, aninput voltage supply and the adjustable voltage divider; and a firstabsorption unit electrically connected to the current mirror andconfigured to absorb a voltage drop from the input voltage supply,wherein the current mirror is configured to generate a first currentsignal and a second current signal wherein the second current signal ismirrored from the first current signal, the first current signal iscontrolled by the third voltage signal, the second current signalcontrols an output voltage supply signal, and the adjustable voltagedivider controls the second voltage signal.
 11. The voltage supply unitof claim 10, wherein the regulator unit comprises an operationalamplifier, wherein a first terminal of the operational amplifier isconfigured to receive the first voltage signal, a second terminal of theoperational amplifier is electrically connected to the adjustablevoltage divider and is configured to receive the second voltage signal,and a third terminal of the operational amplifier is configured tooutput the third voltage signal.
 12. The voltage supply unit of claim 10wherein the first absorption unit comprises a first P-type transistorcomprising: a first terminal configured to receive the first currentsignal from the current mirror, a second terminal electrically connectedto a second p-type transistor, a third terminal electrically connectedto the second P-type transistor, and a fourth terminal electricallyconnected to the first terminal of the first P-type transistor.
 13. Thevoltage supply unit of claim 10, further comprising a second absorptionunit, wherein the second absorption unit comprises a first diodecomprising: an input node configured to receive the second currentsignal from the current mirror; and an output node electricallyconnected to the adjustable voltage divider.
 14. The voltage supply unitof claim 13, further comprising: a second current mirror; and a thirdabsorption unit electrically connected to the second current mirror andthe output node.
 15. The voltage supply unit of claim 14 wherein thethird absorption unit comprises a first P-type transistor and a secondP-type transistor, wherein: a first terminal of the first P-typetransistor is electrically connected to the output node, a secondterminal of the first P-type transistor is electrically connected to thesecond P-type transistor, a third terminal of the first P-typetransistor is electrically connected to the second terminal of the firstP-type transistor, and a fourth terminal of the first P-type transistoris electrically connected to the first terminal of the first P-typetransistor, and wherein the second p-type transistor is electricallyconnected to the second current mirror.
 16. The voltage supply unit ofclaim 14, further comprising an N-type transistor, wherein: a firstterminal of the N-type transistor is configured as a first input node toreceive a first bias voltage signal, a second terminal of the N-typetransistor is configured as a second input node to receive a thirdcurrent signal from the third absorption unit, and a third terminal ofthe N-type transistor is electrically connected to the second currentmirror.
 17. A method of generating an output voltage level from an inputvoltage level in a voltage supply unit, the method comprising:controlling a first current signal of a current mirror by a firstoperating voltage of a regulator unit; absorbing a voltage drop along aconductive path from the current mirror to a cascode unit; controlling afirst operating voltage of the current mirror by the first currentsignal; controlling a second operating voltage of the current mirror bythe first operating voltage of the current mirror; controlling a secondcurrent signal of the current mirror by the second operating voltage ofthe current mirror; and generating the output voltage level based on thesecond current signal.
 18. The method of claim 17, wherein controlling afirst operating voltage of a regulator unit comprises: receiving a firstvoltage signal, wherein the first voltage signal is a reference voltagesignal; receiving a second voltage signal, wherein the second voltagesignal is a feedback voltage signal; and generating the first operatingvoltage of the regulator unit based on the first voltage signal and thesecond voltage signal.
 19. The method of claim 17 wherein the voltagedrop is absorbed by a P-type transistor.
 20. The method of claim 17,further comprising: reducing electrical over stress in the voltagesupply unit by controlling a first bias voltage of a first N-typetransistor and controlling a second bias voltage of a second N-typetransistor.